1. Field of the Invention
The present invention relates to a solid-state image sensor, and more particularly, it relates to a solid-state image sensor in which a driver circuit portion for transfer gates and charge transfer devices and a photodetector portion are integrated on the single common semiconductor substrate.
2. Description of the Prior Art
In a conventional CCD (Charge Coupled Device) type solid-stat image sensor, a circuit portion for driving transfer gates and CCDs and a photodetector portion are not integrated on the single common semiconductor substrate. However, a solid-state image sensor such as a CSD (Charge Sweep Device) type solid-state image sensor in which a driver circuit portion for transfer gates and vertical charge transfer devices and a photodetector portion are integrated on the single common semiconductor substrate has been developed in these days. Such a CSD type solid-state image sensor is disclosed in a article by M. Kimata et al., entitled "A 480.times.400 Element Image Sensor with a Charge Sweep Device", IEEE International Solid-State Circuits Conference, Technical Digest, 1985, pp. 100-101; and U.S. Pat. No. 4,581,539.
FIG. 1 is a schematic plan view showing a structure of such a conventional CSD type solid-state image sensor.
A structure of the CSD type solid-state image sensor shown in FIG. 1 is now described.
In FIG. 1, photodetectors 101-103, 111-113 and 121-123, and gate electrodes 201-203, 211-213 and 221-223 for transfer gates (not shown) and vertical charge transfer devices (not shown) are arranged in row and column directions in a two-dimensional manner.
A transfer gate selecting circuit 700 is arranged on one side of an array comprising the photodetectors and the gate electrodes, and a vertical charge transfer device driving circuit 800 is arranged on the other side thereof. The transfer gate selecting circuit 700 and the vertical charge transfer device driving circuit 800 are connected to the gate electrodes 201-203, 211-213 and 221-223, respectively. The transfer gate selecting circuit 700 provides a transfer gate selecting]g signal for selecting a predetermined transfer gate. The vertical charge transfer device driving circuit 800 provides a vertical charge transfer device driving signal for driving a vertical charge transfer device.
In addition, storage gates 300, 310 and 320 for temporarily storing signal charges from the vertical charge transfer devices are linearly arranged on a further side of the array comprising the photodetectors and the gate electrodes (on the lower side of the array in FIG. 1). Storage control gates 400, 410 and 420 are linearly arranged on the still lower side of the array of the storage gates. Furthermore, a horizontal CCD 500 and an output preamplifier 600 are arranged on the lower side of the array of the storage control gates. The storage control gates 400, 410 and 420 control transfer of signal charges from the storage gates 300, 310 and 320 to the horizontal CCD 500. A photodetector portion comprises the photodetectors 101-103, 111-113 and 121-123, the gate electrodes 201-203, 211-213 and 221-223, transfer gates (not shown), vertical charge transfer devices (not shown), the storage gates 300, 310 and 320, the storage control gates 400, 410 and 420, the vertical CCD 500 and the output preamplifier 600. On the other hand, a driver circuit portion comprises the transfer gate selecting circuit 700 and the vertical charge transfer device driving circuit 800. The photodetector portion and the driver circuit portion are formed on the single common semiconductor substrate.
FIG. 2 is a cross sectional view of one pixel of the CSD type solid-state image sensor shown in FIG. 1. In FIG. 2, a thick oxide film 2 for isolating elements is formed on a p-type semiconductor substrate 1. An n-type impurity region 6 is formed in a region on the p-type semiconductor substrate 1, defined by the oxide film 2. The p-type semiconductor substrate 1 and the n-type impurity region 6 constitute the photodetector 101 having pn junction formed therebetween. In addition, an n-type impurity region 3 is formed on the p-type semiconductor substrate 1, and a p.sup.+ -type impurity region 4 is formed on the p-type semiconductor substrate 1 between the n-type impurity regions 3 and 6. Furthermore, a gate oxide film 5 is formed on the n-type impurity region 3, the p.sup.+ -type impurity region 4 and the n-type impurity region 6, and the gate electrode 201 is formed on the portion on the gate oxide film 5, extending over the n-type impurity region 3 and the p.sup.+ -type impurity region 4. The p.sup.+ -type impurity region 4, the gate oxide film 5 and the gate electrode 201 constitute a transfer gate 7. A channel of a desired potential is formed on the p.sup.+ -type impurity region 4 immediately under the gate insulator film 5, in accordance with a transfer gate selecting signal applied to the gate electrode 201 from the transfer gate selecting circuit 700 (FIG. 1), so that the transfer gate 7 reads out signal charges from the photodetector 101. On the other hand, the n-type impurity region 3, the gate oxide film 5 and the gate electrode 201 constitute a vertical charge transfer device 8. A transfer channel of a desired potential is formed in a part of the n-type impurity region 3, in accordance with a vertical charge transfer device driving signal applied to the gate electrode 201 from the vertical charge transfer device driving circuit 800 (FIG. 1), so that the vertical charge transfer device 8 receives signal charges from a transfer gate and transfers the signal charges in a predetermined direction (in a vertical direction).
FIG. 3 is a diagram showing change in channel potential of the transfer gate 7 and the vertical charge transfer device 8 when the voltage (the gate voltage) applied to the gate electrode 201 is changed in a conventional CSD type solid-state image sensor having the structure shown in FIG. 2.
Referring now to FIG. 3, operation of the conventional CSD type solid-state image sensor shown in FIG. 2 is described. Since basic operation of the entire CSD type solid-state image sensor is described in detail in the above described document, it is omitted except for operation of read-out of signal charges from a photodetector related to the present invention.
In FIG. 3, .phi..sub.OF is a potential on the photodetector 101 when an overflow drain, if any, for removing excess charges of the photodetector 101 operates.
When signal charges are transferred in the vertical charge transfer device 8, the voltage applied to the gate electrode 201 changes between V.sub.G1 and V.sub.G2. Correspondingly, the potential of a transfer channel formed in a part of the n-type impurity region 3 for the vertical charge transfer device 8 changes between .phi..sub.C1 and .phi..sub.C2.
Since a photodetector portion and a driver circuit portion are formed on the single common p-type semiconductor substrate 1 and hence the substrate potentials of the driver circuit portion and the photodetector portion are equal, the gate potential V.sub.G1 can be lowered only to the substrate potentials (OV in this case) at minimum. When the gate voltage is between V.sub.G1 and v.sub.G2, the transfer gate 7 is always turned "off", so that signal charges are not read out into the vertical charge transfer device 8 from the photodetector 101. Signal charges are read out from the photodetector 101 by raising the gate voltage to V.sub.G3 which is higher than V.sub.G2. The channel potential of the vertical charge transfer device 8 becomes .phi..sub.C3, and the channel potential of the transfer gate 7 becomes .phi..sub.T3, so that the potential of the photodetector 101 is reset to .phi..sub.T3.
Since a conventional CSD type solid-state image sensor is constructed as described above, there exist following disadvantages. More particularly, in order that signal charges may not be read out from the photodetector 101 when signal charges are transferred in the vertical charge transfer device 8, the threshold voltage of the transfer gate 7 must be higher than the voltage at an "H" level of a vertical charge transfer device driving signal In addition, in order that signal charges may be sufficiently read out from the photodetector 101 by turning the transfer gate 7 "on", the voltage of a transfer gate selecting signal must be made very high.